SH7080_09 Datasheet, PDF (396/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Mode register setting timing is shown in figure 9.30. A PALL command (all bank precharge
command) is firstly issued. An REF command (auto-refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the WTRP[1:0] bits in CS3WCR, are inserted between the PALL and the first REF.
Idle cycles, of which number is specified by the WTRC[1:0] bits in CS3WCR, are inserted
between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one
or more, are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM after power-on before issuing PALL
command. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse
width of the reset signal is longer than the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.
Tp
Tpw
Trr
Trc
PALL
REF
CK
Trc
Trr
Trc
REF
Trc Tmw Tnop
MRS
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
Hi-Z
BS
DACKn*²
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.30 SDRAM Mode Register Write Timing (Based on JEDEC)
Rev. 4.00 Dec. 15, 2009 Page 336 of 1558
REJ09B0181-0400