English
Language : 

SH7080_09 Datasheet, PDF (40/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family
Section 13 Port Output Enable (POE)
Figure 13.1 Block Diagram of POE .......................................................................................... 680
Figure 13.2 Falling Edge Detection........................................................................................... 707
Figure 13.3 Low-Level Detection Operation............................................................................. 708
Figure 13.4 Output-Level Compare Operation.......................................................................... 708
Figure 13.5 Pin State when a Power-On Reset is Issued from the Watchdog Timer ................ 711
Section 14 Watchdog Timer (WDT)
Figure 14.1 Block Diagram of WDT......................................................................................... 714
Figure 14.2 Writing to WTCNT and WTCSR........................................................................... 719
Figure 14.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock is
Specified to Pφ/32 by CKS2 to CKS0) .................................................................. 721
Section 15 Serial Communication Interface (SCI)
Figure 15.1 Block Diagram of SCI............................................................................................ 724
Figure 15.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits) ........................................................... 756
Figure 15.3 Sample Flowchart for SCI Initialization ................................................................ 759
Figure 15.4 Sample Flowchart for Transmitting Serial Data..................................................... 760
Figure 15.5 Example of Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) .......................................................................... 762
Figure 15.6 Sample Flowchart for Receiving Serial Data (1) ................................................... 763
Figure 15.6 Sample Flowchart for Receiving Serial Data (2) ................................................... 764
Figure 15.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit)................. 766
Figure 15.8 Data Format in Clock Synchronous Communication............................................. 766
Figure 15.9 Sample Flowchart for SCI Initialization ................................................................ 768
Figure 15.10 Sample Flowchart for Transmitting Serial Data..................................................... 769
Figure 15.11 Example of SCI Transmit Operation...................................................................... 770
Figure 15.12 Sample Flowchart for Receiving Serial Data (1) ................................................... 771
Figure 15.12 Sample Flowchart for Receiving Serial Data (2) ................................................... 772
Figure 15.13 Example of SCI Receive Operation ....................................................................... 773
Figure 15.14 Sample Flowchart for Transmitting/Receiving Serial Data ................................... 774
Figure 15.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ........................................... 776
Figure 15.16 Sample Multiprocessor Serial Transmission Flowchart......................................... 777
Figure 15.17 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit).......................................................................... 778
Figure 15.18 Sample Multiprocessor Serial Reception Flowchart (1) ........................................ 779
Figure 15.18 Sample Multiprocessor Serial Reception Flowchart (2) ........................................ 780
Figure 15.19 SCKIO Bit, SCKDT bit, and SCK Pin ................................................................... 782
Rev. 4.00 Dec. 15, 2009 Page xxxviii of lviii
REJ09B0181-0400