SH7080_09 Datasheet, PDF (456/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can be
done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI interrupt
was input.
0: No NMI interrupt
[Clearing condition]
• Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
Note: If the NMIF bit is read at the same point in time that it
is set to 1, in some cases the read value will be 0 but
the internal state will be as if it was read as 1.
Therefore, subsequently writing 0 to NMIF will clear it
to 0 in the same way as writing 0 to the flag after
reading it as 1. To prevent the NMIF bit from being
cleared to 0 inadvertently, always write 1 to the NMIF
bit except in cases when explicitly clearing it. To
explicitly clear the NMIF bit, write 0 to it after reading
it as 1. Note that if the NMIF bit is not used, there is
no problem with always writing 0 to it (and writing 0 to
it after reading it as 1 explicitly to clear it).
0
DME
0
R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, transfer is
enabled. In this time, all of the bits TE in CHCR, NMIF, and
AE in DMAOR must be 0. If this bit is cleared during
transfer, transfers in all channels are terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
10.3.6 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit readable/writable register that specifies the timing of bus release. It also sets
the function to perform transfer by the DMAC preferentially. For details, see section 9.4.8, Bus
Function Extending Register (BSCEHR).
Rev. 4.00 Dec. 15, 2009 Page 396 of 1558
REJ09B0181-0400