SH7080_09 Datasheet, PDF (428/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
BSC Register Setting*¹
CMNCR.DMAIW
Setting
CS3WCR.WTRP
Setting
CS3WCR.TRWL
Setting
Minimum Number of
Idle Cycles
4
4
2
5
4
4
3
6
Notes: DMAC is driven by Bφ. The minimum number of idle cycles is not affected by changing a
clock ratio.
1. For single address mode transfer from the external device with DACK to the SDRAM
interface, the minimum number of idle cycles is not affected by the IWW, IWRWD,
IWRWS, IWRRD, and IWRRS bits in CSnBCR.
2. Set the WTRCD bits to select 1 cycle or less.
Rev. 4.00 Dec. 15, 2009 Page 368 of 1558
REJ09B0181-0400