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| SH7080_09 Datasheet, PDF (1486/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family | |||
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Section 28 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
tAD1
tAD1
A29 to A0
CSn
WRxx
tCSD
tRWD
tWSD1
tWSD1
tCSD
tRWD
RDWR
Read
RD
D31 to D0
tRWD
tRSD
tOE
tACC
tRSD
tRDS1
tRDH1
tRWD
RDWR
Write
D31 to D0
BS
DACKn*
TENDn*
tWDD1
tBSD
tDACD
tBSD
tWTH
tWTH
WAIT
tWTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
tWDH1
tDACD
Figure 28.16 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 0
(UB/LB in Write Cycle Controlled))
Rev. 4.00 Dec. 15, 2009 Page 1426 of 1558
REJ09B0181-0400
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