SH7080_09 Datasheet, PDF (890/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.13 SCSMR Settings and SCIF Communication Formats
SCSMR Settings
Bit 7 Bit 6 Bit 5 Bit 3
C/A CHR PE STOP Mode
0
0
00
Asynchronous
1
10
1
1
00
1
10
1
1
x
xx
Clock
synchronous
[Legend]
x:
Don't care
SCIF Communication Format
Data Length
8-bit
Parity Bit
Not set
Set
7-bit
Not set
Set
8-bit
Not set
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
None
Table 16.14 SCSMR and SCSCR Settings and SCIF Clock Source Selection
SCSMR SCSCR Settings
SCIF Transmit/Receive Clock
Bit 7
C/A
Bit 1 Bit 0
CKE1 CKE0 Mode
Clock
Source SCK Pin Function
0
0
0
Asynchronous Internal SCIF does not use the SCK pin. The state
of the SCK pin depends on both the SCKIO
and SCKDT bits.
1
Clock with a frequency 16 times the bit rate
is output.
1
0
External Input a clock with frequency 16 times the
bit rate.
1
⎯
Setting prohibited.
1
0
x
Clock
Internal Serial clock is output.
1
0
synchronous _{External Input the serial clock.}
1
⎯
Setting prohibited.
[Legend]
x:
Don't care
Rev. 4.00 Dec. 15, 2009 Page 830 of 1558
REJ09B0181-0400