SH7080_09 Datasheet, PDF (955/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 17.15 shows an example of reception operation, and figure 17.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When setting the SSU to slave mode to perform continuous reception, read SSRDR before starting
the next receive operation. If the next receive operation starts before SSRDR is read and RDRF is
cleared to 0, the integrity of subsequent data cannot be guaranteed.
SSCK
SSO
RDRF
Bit 0
1 frame
Bit 7
Bit 0
1 frame
Bit 7
Bit 0
Bit 7
LSI operation
User operation Dummy-read SSRDR
RXI interrupt
generated
RXI interrupt
generated
Read data from SSRDR
RXI interrupt
generated
Read data from SSRDR
Figure 17.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
Rev. 4.00 Dec. 15, 2009 Page 895 of 1558
REJ09B0181-0400