SH7080_09 Datasheet, PDF (222/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
3. When data access (address only) is specified as a break condition:
The address of the instruction immediately after the instruction that matched the break
condition is saved in the stack. The instruction that matches the condition is executed, and the
user break occurs before the next instruction is executed. However when a delay slot
instruction matches the condition, the branch destination address is saved in the stack.
4. When data access (address + data) is specified as a break condition:
When a data value is added to the break conditions, the address of an instruction that is within
two instructions of the instruction that matched the break condition is saved in the stack. At
which instruction the user break occurs cannot be determined accurately.
When a delay slot instruction matches the condition, the branch destination address is saved in
the stack. If the instruction following the instruction that matches the break condition is a
branch instruction, the user break may occur after the branch instruction or delay slot has
finished. In this case, the branch destination address is saved in the stack.
7.4.6 PC Trace
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
⎯ If a branch occurs due to a branch instruction, the address of the branch instruction is saved
in BRSR and the address of the branch destination instruction is saved in BRDR.
⎯ If a branch occurs due to an interrupt or exception, the value saved in stack due to
exception occurrence is saved in BRSR and the start address of the exception handling
routine is saved in BRDR.
3. BRSR and BRDR have four pairs of queue structures (eight pairs for the F-ZTAT version
supporting full functions of E10A). The top of queues is read first when the address stored in
the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR
in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off
and on, the values in the queues are invalid.
4. Since four pairs (eight pairs for the F-ZTAT version supporting full functions of E10A) of
queue are shared with the AUD, set the PCTE bit in BRCR to 1 after setting the MSTP25 bit in
STBCR5 to 0 and the AUDSRST bit in STBCR6 to 1. Although the AUD is only available in
the F-ZTAT version supporting full functions of the E10A, this setting should also be made in
the normal F-ZTAT version.
Rev. 4.00 Dec. 15, 2009 Page 162 of 1558
REJ09B0181-0400