SH7080_09 Datasheet, PDF (303/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
5
DMAIWA 0
R/W Specification for Method of Inserting Wait States
between Access Cycles during DMA Single Address
Transfer
Specifies the method of inserting the idle cycles
specified by the DMAIW1 and DMAIW0 bits. Clearing
this bit will make this LSI insert the idle cycles when
another device, which includes this LSI, drives the data
bus after an external device with DACK drove it. When
the external device with DACK drives the data bus
continuously, idle cycles are not inserted. Setting this bit
will make this LSI insert the idle cycles after one access
is completed even when the continuous accesses to an
external device with DACK are performed.
0: Idle cycles are inserted when another device drives
data bus after external device with DACK drives data
bus
1: Idle cycles are always inserted after external device
with DACK is accessed.
4
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
3, 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
HIZMEM 0
R/W Hi-Z Memory Control
Specifies the pin state in software standby mode for
A29 to A0, BS, CSn, RDWR, WRxx, RD, AH, FRAME,
ICIORD, ICIOWR, WE, CE1A, CE1B, CE2A, and
CE2B. While the bus is released, these pins are in high-
impedance state regardless of this bit setting.
0: High impedance in software standby mode
1: Driven in software standby mode
Rev. 4.00 Dec. 15, 2009 Page 243 of 1558
REJ09B0181-0400