SH7080_09 Datasheet, PDF (941/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.4.5 SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1) Initial Settings in SSU Mode
Figure 17.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note:
Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Rev. 4.00 Dec. 15, 2009 Page 881 of 1558
REJ09B0181-0400