SH7080_09 Datasheet, PDF (1043/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 20 Compare Match Timer (CMT)
20.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 20.6 shows the
timing to write to CMCNT in words.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
CMCNT count-up
enable
CMCNT
N
M (CMCNT write data)
Figure 20.6 Conflict between Word-Write and Count-Up Processes of CMCNT
Rev. 4.00 Dec. 15, 2009 Page 983 of 1558
REJ09B0181-0400