SH7080_09 Datasheet, PDF (948/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Dummy-read SSRDR
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes [3]
No
[4]
Consecutive data reception? ^No
Yes
Read received data in SSRDR
RDRF automatically cleared
[1] Initial setting:
Specify the receive data format.
[2] Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
[4] To continue single reception:
When continuing single reception, wait for time of t_SUcyc
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
[5] To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
[5]
RE = 0
Read receive data in SSRDR
End reception
[6]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.8 Flowchart Example of Data Reception (SSU Mode)
(4) Data Transmission/Reception
Figure 17.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
Rev. 4.00 Dec. 15, 2009 Page 888 of 1558
REJ09B0181-0400