SH7080_09 Datasheet, PDF (861/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
2
⎯
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKE[1:0] 00
R/W Clock Enable 1 and 0
Select the SCIF clock source and enable or disable
clock output from the SCK pin. Depending on the
combination of CKE1 and CKE0, the SCK pin can be
used for serial clock output or serial clock input.
The CKE0 setting is valid only when the SCIF is
operating on the internal clock (CKE1 = 0). The CKE0
setting is ignored when an external clock source is
selected (CKE1 = 1). In clock synchronous mode, select
the SCIF operating mode in the serial mode register
(SCSMR), then set CKE1 and CKE0.
• Asynchronous mode
00: Internal clock, SCK pin used for input pin (The input
signal is ignored. The state of the SCK pin depends
on both the SCKIO and SCKDT bits.)
01: Internal clock, SCK pin used for clock output
(The output clock frequency is 16 times the bit rate.)
10: External clock, SCK pin used for clock input
(The input clock frequency is 16 times the bit rate.)
11: Setting prohibited
• Clock synchronous mode
00: Internal clock, SCK pin used for serial clock output
01: Internal clock, SCK pin used for serial clock output
10: External clock, SCK pin used for serial clock input
11: Setting prohibited
Rev. 4.00 Dec. 15, 2009 Page 801 of 1558
REJ09B0181-0400