SH7080_09 Datasheet, PDF (782/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 14 Watchdog Timer (WDT)
14.5 Usage Note
14.5.1 WTCNT Setting Value
If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT changes
from H'FF to H'00 after one cycle of count clock, but overflow occurs when WTCNT changes
from H'FF to H'00 after 257 cycles of count clock.
If WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from
H'FF to H'00 after one cycle of count clock.
Rev. 4.00 Dec. 15, 2009 Page 722 of 1558
REJ09B0181-0400