SH7080_09 Datasheet, PDF (322/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
8, 7
A3CL[1:0] 10
R/W CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6, 5
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4, 3
TRWL[1:0] 00
R/W Number of Wait Cycles for Precharge Activation
Specify the minimum number of wait cycles to be
inserted for activation of precharge.
• From issuance of WRITA command by this LSI until
auto precharge is activated in SDRAM:
ACTV command is issued for the same bank in non-
bank active mode.
See the datasheet of the SDRAM to find the number
of cycles taken from the acceptance of WRITA
command by SDRAM until auto-precharge is
activated. These bits should be set so that the
above number of cycles will not exceed the number
of cycles specified by these bits.
• From issuance of WRIT command by this LSI until
issuance of PRE command:
Different row addresses in the same bank are
accessed in bank active mode.
The setting for areas 2 and 3 is common.
00: 0 cycle (No wait cycles)
01: 1 cycle
10: 2 cycles
11: 3 cycles
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 262 of 1558
REJ09B0181-0400