SH7080_09 Datasheet, PDF (272/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for re-
setting the transfer destination address for the first data transfer. Use the upper eight bits of
DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.
If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits
of the transfer destination address for the first data transfer to H'21. The lower 16 bits of the
transfer destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper eight bits of the transfer destination address for the first
data transfer to H'20. The lower 16 bits of the transfer destination address of the first data
transfer and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
no interrupt request is sent to the CPU.
Input circuit
Transfer information
located on the on-chip memory
Input buffer
1st data transfer
information
2nd data transfer
information
Chain transfer
(counter = 0)
Upper 8 bits of DAR
Figure 8.19 Chain Transfer when Counter = 0
Rev. 4.00 Dec. 15, 2009 Page 212 of 1558
REJ09B0181-0400