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SH7080_09 Datasheet, PDF (1581/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family
Appendix
External Space (Burst ROM (Clock Synchronous))
32-bit Space
Pin Name
WE
Most
Significant Second
Byte
Byte
RH
H
Least
Significant Upper
Third Byte Byte
Word
H
H
H
Lower
Word
H
W⎯
⎯
⎯
⎯
⎯
⎯
ICIOWR
RH
H
H
H
H
H
W⎯
⎯
⎯
⎯
⎯
⎯
A29 to A0
Address Address Address Address Address Address
D31 to D24
Data
Hi-Z
Hi-Z
Hi-Z
Data
Hi-Z
D23 to D16
Hi-Z
Data
Hi-Z
Hi-Z
Data
Hi-Z
D15 to D8
Hi-Z
Hi-Z
Data
Hi-Z
Hi-Z
Data
D7 to D0
Hi-Z
Hi-Z
Hi-Z
Data
Hi-Z
Data
[Legend]
R:
W:
Enabled:
Read
Write
Chip select signals corresponding to accessed areas = Low.
The other chip select signals = High.
Longword
H
⎯
H
⎯
Address
Data
Data
Data
Data
Table C.1 Pin States of Bus Related Signals (10)
Pin Name
CS0 to CS8
CE1A, CE1B,
CE2A, CE2B
BS
RASU, RASL
CASU, CASL
DQMUU
DQMUL
DQMLU
DQMLL
Upper Byte
Enabled*1
H
L
Enabled*2
Enabled*2
H
H
L
H
External Space (SDRAM)
16-bit Space
Lower Byte
Word/Longword
Enabled*1
Enabled*1
H
H
L
Enabled*2
Enabled*2
H
H
H
L
L
Enabled*2
Enabled*2
H
H
L
L
Rev. 4.00 Dec. 15, 2009 Page 1521 of 1558
REJ09B0181-0400