SH7080_09 Datasheet, PDF (1496/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
CK
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
A25 to A0
Row
address
Column
address
A12/A11^*1
t_AD1
t_AD1
READ command
t_AD1
t_AD1
READA
command
CSn
RDWR
RASx
CASx
DQMxx
t_CSD
t_RWD
t_RASD
t_RASD
t_CASD
t_DQMD
D31 to D0
t_BSD
BS
t_CSD
t_RWD
t_CASD
t_DQMD
t_RDS2 t_RDH2
t_RDS2 t_RDH2
t_BSD
CKE
DACKn^*2
TENDn^*2
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1436 of 1558
REJ09B0181-0400