SH7080_09 Datasheet, PDF (868/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
1
RDF
0
R/(W)* Receive FIFO Data Full
Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the
number of data in SCFRDR has become more than
the receive trigger number specified by the RTRG1
and RTRG0 bits in the FIFO control register
(SCFCR).
0: The number of transmit data written to SCFRDR is
less than the specified receive trigger number
[Clearing conditions]
• RDF is cleared to 0 by a power-on reset
• RDF is cleared to 0 when the SCFRDR is read
until the number of receive data in SCFRDR
becomes less than the specified receive trigger
number after 1 is read from RDF and then 0 is
written
• RDF is cleared to 0 when the SCFRDR is read by
using the DTC until the number of receive data in
SCFRDR becomes less than the specified receive
trigger number
1: The number of receive data in SCFRDR is more
than the specified receive trigger number
[Setting condition]
• RDF is set to 1 when a number of receive data
more than the specified receive trigger number is
stored in SCFRDR*
Note: * SCFTDR is a 16-byte FIFO register. When
RDF is 1, the specified receive trigger
number of data can be read at the maximum.
If an attempt is made to read after all the data
in SCFRDR has been read, the data is
undefined. The number of receive data in
SCFRDR is indicated by the lower 8 bits of
SCFDR.
Rev. 4.00 Dec. 15, 2009 Page 808 of 1558
REJ09B0181-0400