SH7080_09 Datasheet, PDF (200/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAMA31 to All 0
BAMA 0
R/W Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
Note: n = 31 to 0
7.3.3 Break Bus Cycle Register A (BBRA)
BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel A.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
- CPA2* CPA1* CPA0* CDA1* CDA0 IDA1* IDA0 RWA1* RWA0 SZA1* SZA0*
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0.
The write value should always be 0.
Initial
Bit
Bit Name Value R/W Description
15 to 11 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
CPA2*
0
9
CPA1*
0
8
CPA0*
0
R/W Bus Master Select A for I Bus
R/W Select the bus master when the I bus is selected as the
R/W ^{bus cycle of the channel A break condition. However,}
when the L bus is selected as the bus cycle, the setting
of the CPA2 to CPA0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: The DMAC cycle is included in the break condition
1xx: The DTC cycle is included in the break condition
Rev. 4.00 Dec. 15, 2009 Page 140 of 1558
REJ09B0181-0400