SH7080_09 Datasheet, PDF (622/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
9. Initial Output in Complementary PWM Mode
In complementary PWM mode, the initial output is determined by the setting of bits OLSN
and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to
OLS3P in timer output control register 2 (TOCR2).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set
in the dead time register (TDDR). Figure 11.44 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR
value is shown in figure 11.45.
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3 and TCNT_4 values
TGRA_4
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
Initial output
Dead time
Active level
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3 and TCNT_4 count start
(TSTR setting)
Figure 11.44 Example of Initial Output in Complementary PWM Mode (1)
Rev. 4.00 Dec. 15, 2009 Page 562 of 1558
REJ09B0181-0400