SH7080_09 Datasheet, PDF (1603/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
16.3.9 FIFO Control
Register (SCFCR)
17.3.1 SS Control
Register H (SSCRH)
17.3.2 SS Control
Register L (SSCRL)
17.3.5 SS Status
Register (SSSR)
Page
823
864
865
870
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name value
3
MCE
0
R/W Description
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In clock synchronous mode, clear this bit to 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * Regardless of the input value, the CTS level
has no effect on transmit operation and the
RTS level has no effect on receive operation.
Table amended
Initial
Bit Bit Name Value R/W
1, 0 CSS[1:0] 01
R/W
Description
SCS Pin Select
Select that the SCS pin functions as SCS input or
output.
00: Setting prohibited
01: Setting prohibited
10: Function as SCS automatic input/output (function as
SCS input before and after transfer and output a
low level during transfer)
11: Function as SCS automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
Table amended
Initial
Bit
Bit Name Value R/W
7
FCLRM 0
R/W
Description
Flag Clear Mode
Selects whether the SSRXI and SSTXI interrupt flags
are cleared on writing to SSTDR or reading from
SSRDR or on completion of DTC transfer. When using
the DTC, set this bit to 0.
0: Flags are cleared when DTC transfer is completed
(except when transfer counter value is H'0000)
1: Flags are cleared on SSTDR or SSRDR access
Table amended
Initial
Bit
Bit Name Value R/W
2
TDRE
1
R/W
Description
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
• When the DTC is activated by an SSTXI interrupt
and transmit data is written to SSTDR while the
DISEL bit in MRB of the DTC is 0 (except when
DTC transfer counter value is H'0000)
Rev. 4.00 Dec. 15, 2009 Page 1543 of 1558
REJ09B0181-0400