SH7080_09 Datasheet, PDF (52/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Table 9.23
Table 9.24
Table 9.24
Table 9.25
Table 9.25
Table 9.26
Table 9.27
Table 9.28
Table 9.29
Table 9.30
Table 9.31
Table 9.32
Table 9.33
Table 9.34
Table 9.35
Table 9.36
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (4)-2 ........................... 312
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-1 ........................... 313
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-2 ........................... 314
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (6)-1 ........................... 315
Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (6)-2 ........................... 316
Relationship between Access Size and Number of Bursts ...................................... 317
Access Address in SDRAM Mode Register Write.................................................. 335
Relationship between Bus Width, Access Size, and Number of Bursts .................. 338
Minimum Number of Idle Cycles between CPU Access Cycles
in Normal Space Interface....................................................................................... 359
Minimum Number of Idle Cycles between Access Cycles during DMAC
Dual Address Mode and DTC Transfer for the Normal Space Interface ................ 360
Minimum Number of Idle Cycles during DMAC Single Address Mode
Transfer to the Normal Space Interface from the External Device with DACK ..... 361
Minimum Number of Idle Cycles between Access Cycles of CPU,
the DMAC Dual Address Mode, and DTC for the SDRAM Interface.................... 363
Minimum Number of Idle Cycles between Access Cycles of the DMAC
Single Address Mode for the SDRAM Interface (1)............................................... 366
Minimum Number of Idle Cycles between Access Cycles of the DMAC
Single Address Mode for the SDRAM Interface (2)............................................... 369
Number of Cycles for Access to On-Chip Peripheral I/O Registers ....................... 378
Number of External Access Cycles......................................................................... 380
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1 Pin Configuration .................................................................................................... 385
Table 10.2 Register Configuration ............................................................................................ 386
Table 10.3 Selecting External Request Modes with RS Bits .................................................... 399
Table 10.4 Selecting External Request Detection with DL, DS Bits ........................................ 400
Table 10.5 Selecting External Request Detection with DO Bit ................................................ 400
Table 10.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ....... 401
Table 10.7 Supported DMA Transfers ...................................................................................... 406
Table 10.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category .................................................................................................................. 413
Table 10.9 Number of Cycles per Access to On-Chip RAM by DMAC .................................. 426
Rev. 4.00 Dec. 15, 2009 Page l of lviii
REJ09B0181-0400