SH7080_09 Datasheet, PDF (188/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 6 Interrupt Controller (INTC)
Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt source that should have been cleared is not inadvertently accepted again, read the
interrupt source flag after it has been cleared, confirm that it has been cleared, and then
execute an RTE instruction.
* Interrupt requests that are designated as edge-detect type are held pending until the
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ status register (IRQSR). Interrupts held pending due to edge detection are
cleared by a power-on reset or a manual reset.
Rev. 4.00 Dec. 15, 2009 Page 128 of 1558
REJ09B0181-0400