SH7080_09 Datasheet, PDF (306/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
21
20, 19
18
17, 16
15
Bit Name
⎯
Initial
Value R/W
0
R
IWRRD[1:0] 11
R/W
⎯
0
R
IWRRS[1:0] 11
R/W
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Read
Cycles in Different Spaces
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-read cycles in
different spaces.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Read-Read
Cycles in the Same Space
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are continuous read-read cycles in the
same space.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 246 of 1558
REJ09B0181-0400