SH7080_09 Datasheet, PDF (1525/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
28.3.11 Synchronous Serial Communication Unit (SSU) Timing
Table 28.16 Synchronous Serial Communication Unit (SSU) Timing
Conditions: V_CC = 3.0 V to 3.6 V or 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, AV_ref = 4.0 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +85°C (consumer applications),
T_a = –40°C to +85°C (industrial applications)
Item
Symbol Min.
Clock cycle
Master t
4
SUcyc
Slave
4
Clock high pulse width
Master
t_HI
60
Slave
60
Clock low pulse width
Master
t_LO
60
Slave
60
Clock rise time
t_RISE
⎯
Clock fall time
t_FALL
⎯
Data input setup time
Master
t_SU
25
Slave
30
Data input hold time
Master t
10
H
Slave
10
SCS setup time
Master
t_LEAD
1.5
Slave
1.5
SCS hold time
Master
t_LAG
1.5
Slave
1.5
Data output delay time
Master t
⎯
OD
Slave
⎯
Data output hold time
Master
t_OH
30
Slave
30
Continuous transmission Master t_TD
1.5
delay time
Slave
1.5
Slave access time
t_SA
⎯
Slave out release time
t_REL
⎯
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Max.
256
256
⎯
⎯
⎯
⎯
20
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
40
⎯
⎯
⎯
⎯
1
1
Unit
t
pcyc
ns
ns
ns
ns
ns
ns
t_pcyc
t_pcyc
ns
ns
t_pcyc
t_pcyc
t_pcyc
Reference
Figure
Figures 28.55 to
28.58
Figures 28.57,
28.58
Rev. 4.00 Dec. 15, 2009 Page 1465 of 1558
REJ09B0181-0400