SH7080_09 Datasheet, PDF (227/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Break Condition Specified for I Bus Data Access Cycle:
(Example 3-1)
• Register specifications
BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678,
BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9,
BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address: H'00314154, Address mask: H'00000000
Data:
H'12345678, Data mask: H'FFFFFFFF
Bus cycle: I bus (CPU cycle)/instruction fetch/read (operand size is not included in the
condition)
<Channel B>
Address: H'00055555, Address mask: H'00000000
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: I bus (CPU cycle)/data access/write/byte
On channel A, a user break occurs when instruction fetch is performed for address H'00314156
in the external memory space.
On channel B, a user break occurs when byte data H'7x is written in address H'00055555 in the
external memory space by the CPU.
Rev. 4.00 Dec. 15, 2009 Page 167 of 1558
REJ09B0181-0400