SH7080_09 Datasheet, PDF (755/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 13 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
11, 10 ⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
POE8E
0
R/W*²
POE8 High-Impedance Enable
This bit specifies whether to place the pins in high-
impedance state when the POE8F bit in ICSR3 is set
to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
8
PIE3
0
R/W Port Interrupt Enable 3
This bit enables or disables interrupt requests when the
POE8 bit in ICSR3 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 2 ⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0 POE8M[1:0] 00
R/W*² POE8 mode 1 and 0
These bits select the input mode of the POE8 pin.
00: Accept request on falling edge of POE8 input
01: Accept request when POE8 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE8 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE8 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Rev. 4.00 Dec. 15, 2009 Page 695 of 1558
REJ09B0181-0400