SH7080_09 Datasheet, PDF (1011/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Initial
Bit Bit Name Value
11
TRGE
0
10
⎯
0
9
CONADF 0
8
STC
0
Section 19 A/D Converter (ADC)
R/W Description
R/W Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG, an MTU2 trigger, or an MTU2S trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
When changing the operating mode, first clear the
ADST bit to 0.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W ADF Control
Controls setting of the ADF bit in 2-channel scan
mode. The setting of this bit is valid only when
triggering of A/D conversion is enabled (TRGE = 1) in
2-channel scan mode. The setting of this bit is ignored
in single mode, 4-channel scan mode, or 8-channel
scan mode.
0: The ADF bit is set when A/D conversion started by
the group 0 trigger or group 1 trigger has finished.
1: The ADF bit is set when A/D conversion started by
the group 0 trigger and A/D conversion started by
the group 1 trigger have both finished. Note that the
triggering order has no affect.
When changing the operating mode, first clear the
ADST bit to 0.
R/W State Control
Sets the A/D conversion time in combination with the
CKSL1 and CKSL0 bits.
0: 50 states
1: 64 states
When changing the A/D conversion time, first clear the
ADST bit to 0.
Rev. 4.00 Dec. 15, 2009 Page 951 of 1558
REJ09B0181-0400