SH7080_09 Datasheet, PDF (460/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Table 10.4 Selecting External Request Detection with DL, DS Bits
CHCR_0 to CHCR_3
DL
DS
Detection of External Request
0
0
Low level detection
1
Falling edge detection
1
0
High level detection
1
Rising edge detection
Note: Prior to setting CHCR_0 to CHCR_3, select the DREQ pin function by the pin function
controller (PFC).
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bits in CHCR_0 to CHCR_3 select this overrun 0 or overrun 1.
Table 10.5 Selecting External Request Detection with DO Bit
CHCR_0 to CHCR_3
DO
0
1
External Request
Overrun 0
Overrun 1
Rev. 4.00 Dec. 15, 2009 Page 400 of 1558
REJ09B0181-0400