SH7080_09 Datasheet, PDF (64/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
Items
Specification
Interrupt controller
(INTC)
• Nine external interrupt pins (NMI and IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source
User debugging
interface (H-UDI)
(only in F-ZTAT
version)
• E10A emulator support
Advanced user
•
debugger (AUD)
(only in F-ZTAT
version supporting full
functions of E10A)
E10A emulator support
Clock pulse
generator (CPG)
• Clock mode: Input clock can be selected from external input or crystal
resonator
• Five types of clocks generated:
⎯ CPU clock: Maximum 80 MHz
⎯ Bus clock: Maximum 40 MHz
⎯ Peripheral clock: Maximum 40 MHz
⎯ MTU2 clock: Maximum 40 MHz
⎯ MTU2S clock: Maximum 80 MHz
Watchdog timer
(WDT)
• On-chip one-channel watchdog timer
• Interrupt generation is supported.
Rev. 4.00 Dec. 15, 2009 Page 4 of 1558
REJ09B0181-0400