SH7080_09 Datasheet, PDF (313/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
21
SZSEL 0
R/W MPX-I/O Interface Bus Width Specification
Specifies the address bit to select the bus width when
the BSZ1 and BSZ0 bits in CS5BCR are set to 11. This
setting is valid only when MPX-I/O is selected for area
5.
0: Address A14 selects the bus width
1: Address A21 selects the bus width
The following shows bus width selection through the
SZSEL bit and A14 or A21.
SZSEL A14
A21
Bus Width
0
0
No effect 8 bits
0
1
No effect 16 bits
1
No effect 0
8 bits
1
No effect 1
16 bits
20
MPXW 0
19
⎯
0
R/W MPX-I/O Interface Address Wait
This setting is valid only when MPX-I/O is selected for
area 5. This bit specifies insertion of a wait cycle into
the address cycle in MPX-I/O interface.
0: No wait
1: Inserts one wait cycle
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 253 of 1558
REJ09B0181-0400