SH7080_09 Datasheet, PDF (118/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 3 MCU Operating Modes
3.4 Address Map
The address map for the operating modes is shown in figures 3.1 to 3.7.
H'00000000
Modes 0 and 1
On-chip ROM disabled mode
H'00000000
Mode 2
On-chip ROM enabled mode
H'00000000
Mode 3
Single chip mode
CS0 space
H'01FFFFFF
H'02000000
H'0BFFFFFF
H'0C000000
H'0DFFFFFF
H'0E000000
Reserved area
CS3 space
Reserved area
H'1BFFFFFF
H'1C000000
H'1DFFFFFF
H'1E000000
CS7 space
On-chip ROM (256 kbytes)
On-chip ROM (256 kbytes)
H'0003FFFF
H'00040000
H'01FFFFFF
H'02000000
H'03FFFFFF
H'04000000
H'0BFFFFFF
H'0C000000
H'0DFFFFFF
H'0E000000
Reserved area
CS0 space
Reserved area
CS3 space
Reserved area
H'1BFFFFFF
H'1C000000
H'1DFFFFFF
H'1E000000
CS7 space
H'0003FFFF
H'00040000
Reserved area
Reserved area
Reserved area
H'FFF7FFFF
H'FFF80000
H'FFF9FFFF
H'FFFA0000
H'FFFF7FFF
H'FFFF8000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
SDRAM mode setting space
Reserved area
On-chip RAM (16 kbytes)
On-chip peripheral
I/O registers
H'FFF7FFFF
H'FFF80000
H'FFF9FFFF
H'FFFA0000
H'FFFF7FFF
H'FFFF8000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
SDRAM mode setting space
Reserved area
On-chip RAM (16 kbytes)
On-chip peripheral
I/O registers
H'FFFF7FFF
H'FFFF8000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
On-chip RAM (16 kbytes)
On-chip peripheral
I/O registers
Figure 3.1 Address Map for Each Operating Mode in SH7083
(256-Kbyte Flash Memory Version)
Rev. 4.00 Dec. 15, 2009 Page 58 of 1558
REJ09B0181-0400