SH7080_09 Datasheet, PDF (104/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
Instruction
Operation
MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn)
MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn)
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn)
MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign
extension → Rn
MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign
extension → Rn
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn
MOV.B R0,@(disp,GBR) R0 → (disp + GBR)
MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR)
MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR)
MOV.B @(disp,GBR),R0 (disp + GBR) → Sign
extension → R0
MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →
Sign extension → R0
MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0
MOVA @(disp,PC),R0 disp × 4 + PC → R0
MOVT Rn
T → Rn
SWAP.B Rm,Rn
Rm → Swap lowest two
bytes → Rn
SWAP.W Rm,Rn
Rm → Swap two
consecutive words → Rn
XTRCT Rm,Rn
Rm: Middle 32 bits of
Rn → Rn
Code
0000nnnnmmmm0100
0000nnnnmmmm0101
0000nnnnmmmm0110
0000nnnnmmmm1100
0000nnnnmmmm1101
0000nnnnmmmm1110
11000000dddddddd
11000001dddddddd
11000010dddddddd
11000100dddddddd
11000101dddddddd
11000110dddddddd
11000111dddddddd
0000nnnn00101001
0110nnnnmmmm1000
0110nnnnmmmm1001
0010nnnnmmmm1101
Execution
Cycles T Bit
1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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1
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Rev. 4.00 Dec. 15, 2009 Page 44 of 1558
REJ09B0181-0400