SH7080_09 Datasheet, PDF (548/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.15 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0
to 4.
TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5,
TCNTV_5, and TCNTW_5 for channel 5.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
• TSTR
Bit: 7
6
5
4
3
2
1
0
CST4 CST3 -
-
- CST2 CST1 CST0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
CST4
0
6
CST3
0
R/W Counter Start 4 and 3
R/W ^{These bits select operation or stoppage for TCNT.}
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
5 to 3 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 488 of 1558
REJ09B0181-0400