SH7080_09 Datasheet, PDF (348/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.2 Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of
the fact that mainly SRAM without a byte selection will be directly connected. When using
SRAM with a byte-selection pin, see section 9.5.8, SRAM Interface with Byte Selection. Figure
9.2 shows the basic timings of normal space access. A no-wait normal access is completed in two
cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.
T1
T2
CK
A29 to A0
CSn
RDWR
Read
RD
D31 to D0
RDWR
Write
WRxx
D31 to D0
BS
DACKn^*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
Rev. 4.00 Dec. 15, 2009 Page 288 of 1558
REJ09B0181-0400