SH7080_09 Datasheet, PDF (62/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
Table 1.1 Features
Items
CPU
Operating modes
User break controller
(UBC)
On-chip ROM
Specification
• Central processing unit with an internal 32-bit RISC (Reduced
Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between
registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
• C language-oriented 62 basic instructions
Note:
Some specifications on slot illegal instruction exception handling
in this LSI differ from those of the conventional SH-2. For details,
see section 5.8.4, Notes on Slot Illegal Instruction Exception
Handling.
• Operating modes
⎯ Single chip mode
⎯ Extended ROM enabled mode
⎯ Extended ROM disabled mode
• Operating states
⎯ Program execution state
⎯ Exception handling state
⎯ Bus release state
• Power-down modes
⎯ Sleep mode
⎯ Software standby mode
⎯ Deep software standby mode
⎯ Module standby mode
• Addresses, data values, type of access, and data size can all be set as
break conditions
• Supports a sequential break function
• Two break channels
• 256 kbytes or 512 kbytes
Rev. 4.00 Dec. 15, 2009 Page 2 of 1558
REJ09B0181-0400