SH7080_09 Datasheet, PDF (15/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

10.4.4 DMA Transfer Types............................................................................................ 406
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 415
10.4.6 Operation Timing.................................................................................................. 419
10.5 Usage Notes ....................................................................................................................... 421
10.5.1 Notes on Output from DACK Pin......................................................................... 421
10.5.2 DMA Transfer by Peripheral Modules ................................................................. 421
10.5.3 Module Standby Mode Setting ............................................................................. 421
10.5.4 Access to DMAC and DTC Registers through DMAC ........................................ 422
10.5.5 Note on SCI as DMAC Activation Source ........................................................... 422
10.5.6 CHCR Setting ....................................................................................................... 422
10.5.7 Note on Multiple Channel Activation ................................................................... 422
10.5.8 Note on Transfer Request Input ............................................................................ 422
10.5.9 Conflict between NMI Interrupt and DMAC Activation ...................................... 422
10.5.10 Notes on Using Peripheral Module Request Modes ............................................. 423
10.5.11 Number of Cycles per Access to On-Chip RAM by DMAC ................................ 426
10.5.12 Note on DMAC Transfer in Burst Mode when Activation Source is MTU2........ 426
10.5.13 Bus Function Extending Register (BSCEHR) ...................................................... 426
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) ...................................427
11.1 Features.............................................................................................................................. 427
11.2 Input/Output Pins ............................................................................................................... 433
11.3 Register Descriptions ......................................................................................................... 434
11.3.1 Timer Control Register (TCR).............................................................................. 438
11.3.2 Timer Mode Register (TMDR) ............................................................................. 442
11.3.3 Timer I/O Control Register (TIOR) ...................................................................... 445
11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) .................................... 464
11.3.5 Timer Interrupt Enable Register (TIER) ............................................................... 465
11.3.6 Timer Status Register (TSR)................................................................................. 470
11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 478
11.3.8 Timer Input Capture Control Register (TICCR) ................................................... 479
11.3.9 Timer Synchronous Clear Register (TSYCR)....................................................... 481
11.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 483
11.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 486
11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4)................................................................. 486
11.3.13 Timer Counter (TCNT)......................................................................................... 487
11.3.14 Timer General Register (TGR) ............................................................................. 487
11.3.15 Timer Start Register (TSTR) ................................................................................ 488
11.3.16 Timer Synchronous Register (TSYR)................................................................... 490
Rev. 4.00 Dec. 15, 2009 Page xiii of lviii
REJ09B0181-0400