SH7080_09 Datasheet, PDF (275/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.9.10 Conflict between NMI Interrupt and DTC Activation
When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the
NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated.
It takes 1 × Bcyc + 3 × Pcyc for determining DTC stop by NMI, 2 × Bcyc for determining DTC
activation by IRQ, and 1 × Pcyc for determining DTC activation by peripheral modules.
8.9.11 Operation when a DTC Activation Request is Cancelled While in Progress
Once the DTC has accepted an activation request, the DTC does not accept the next activation
request until the sequence of DTC processing that ends with writeback has been completed.
Rev. 4.00 Dec. 15, 2009 Page 215 of 1558
REJ09B0181-0400