SH7080_09 Datasheet, PDF (1489/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

CK
A25 to A0
CSn
RDWR
FRAME
Read D31 to D0
Write D31 to D0
BS
DACKn*
TENDn*
WAIT
RD
Tm1
t_AD1
t_CSD
Tmd1w
t_RWD
t_FMD
t_FMD
t_WDD1
t_WDH1
Address
t_WDD1
t_WDH1
t_WDD1
Address
t_BSD
t_BSD
t_DACD
t_WTH
t_WTS
Section 28 Electrical Characteristics
Tmd1
t_AD1
t_CSD
t_RWD
t_FMD
t_RDS2
Data
Data
t_RDH2
t_WDH1
t_DACD
WRxx
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 28.19 Burst MPX-I/O Interface Bus Cycle Single Read Write
(One Address Cycle, One Software Wait Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1429 of 1558
REJ09B0181-0400