SH7080_09 Datasheet, PDF (57/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Table 21.13 SH7085 Multiplexed Pins (Port E).......................................................................... 996
Table 21.14 SH7086 Multiplexed Pins (Port E).......................................................................... 997
Table 21.15 SH7083/SH7084/SH7085 Multiplexed Pins (Port F).............................................. 998
Table 21.16 SH7086 Multiplexed Pins (Port F) .......................................................................... 999
Table 21.17 SH7083 Pin Functions in Each Operating Mode (1) ............................................. 1000
Table 21.17 SH7083 Pin Functions in Each Operating Mode (2) ............................................. 1004
Table 21.18 SH7084 Pin Functions in Each Operating Mode (1) ............................................. 1008
Table 21.18 SH7084 Pin Functions in Each Operating Mode (2) ............................................. 1012
Table 21.19 SH7085 Pin Functions in Each Operating Mode (1) ............................................. 1016
Table 21.19 SH7085 Pin Functions in Each Operating Mode (2) ............................................. 1021
Table 21.20 SH7086 Pin Functions in Each Operating Mode (1) ............................................. 1026
Table 21.20 SH7086 Pin Functions in Each Operating Mode (2) ............................................. 1032
Table 21.21 Register Configuration .......................................................................................... 1038
Table 21.22 Transmit Forms of Input Functions Allocated to Multiple Pins............................ 1160
Section 22 I/O Ports
Table 22.1 Register Configuration .......................................................................................... 1166
Table 22.2 Port A Data Register (PADR) Read/Write Operations.......................................... 1172
Table 22.3 Register Configuration .......................................................................................... 1178
Table 22.4 Port B Data Register L (PBDRL) Read/Write Operations .................................... 1180
Table 22.5 Register Configuration .......................................................................................... 1185
Table 22.6 Port C Data Register (PCDR) Read/Write Operations .......................................... 1188
Table 22.7 Register Configuration .......................................................................................... 1193
Table 22.8 Port D Data Register (PDDR) Read/Write Operations.......................................... 1196
Table 22.9 Register Configuration .......................................................................................... 1203
Table 22.10 Port E Data Register (PEDR) Read/Write Operations .......................................... 1207
Table 22.11 Register Configuration .......................................................................................... 1212
Table 22.12 Port F Data Register L (PFDRL) Read/Write Operations ..................................... 1214
Section 23 Flash Memory
Table 23.1 (1) Relationship between FWE and MD Pins and Operating Modes
(SH7083 and SH7084)........................................................................................ 1219
Table 23.1 (2) Relationship between FWE and MD Pins and Operating Modes
(SH7085 and SH7086)........................................................................................ 1219
Table 23.2 Comparison of Programming Modes .................................................................... 1220
Table 23.3 Pin Configuration .................................................................................................. 1225
Table 23.4 (1) Register Configuration........................................................................................ 1226
Table 23.4 (2) Parameter Configuration..................................................................................... 1226
Table 23.5 Register/Parameter and Target Mode.................................................................... 1227
Table 23.6 Usable Parameters and Target Modes ................................................................... 1236
Rev. 4.00 Dec. 15, 2009 Page lv of lviii
REJ09B0181-0400