SH7080_09 Datasheet, PDF (397/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.7 Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called burst mode or page mode. In the burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent accesses are performed only by changing the address, without negating the
RD signal at the end of the first cycle. In the second and subsequent accesses, addresses are
changed at the falling edge of the CK.
For the first access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is
inserted. For the second and subsequent access cycles, the number of wait cycles specified by the
BW[1:0] bits in CSnWCR is inserted.
In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access that does not perform the burst operation in the burst ROM (clock
asynchronous) interface, access timing is the same as a normal space.
Table 9.28 lists the relationship between bus width, access size, and the number of bursts. Figure
9.31 shows a timing chart.
Rev. 4.00 Dec. 15, 2009 Page 337 of 1558
REJ09B0181-0400