SH7080_09 Datasheet, PDF (433/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
• When DTC/DMAC activation request is generated during read access to external space from CPU
Internal bus
Read access to external
space from CPU
DTC/DMAC
External bus
DTC/DMAC
activation request
Read access to external
space from CPU
DTC/DMAC activation request is generated in this period.
• When DTC/DMAC activation request is generated during write access to external space from CPU (1)
Internal bus
Write to external
space from CPU
DTC/DMAC
External bus
DTC/DMAC
activation request
Write access to external
space from CPU
DTC/DMAC activation request is generated in this period.
• When DTC/DMAC activation request is generated during write access to external space from CPU (2)
(When external space read request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external
space from CPU
Read access to external
space from CPU
DTC/DMAC
External bus
DTC/DMAC
activation request
Write access to external
space from CPU
Read access to external
space from CPU
DTC/DMAC activation request is generated in this period.
• When DTC/DMAC activation request is generated during write access to external space from CPU (3)
(When external space write request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external Write to external
space 1 from CPU space 2 from CPU
DTC/DMAC
External bus
DTC/DMAC
activation request
Write access to external
space 1 from CPU
Write access to external
space 2 from CPU
DTC/DMAC activation request is generated in this period.
Figure 9.50 Bus Arbitration when DTC or DMAC Activation Request Occurs during
External Space Access from CPU
Rev. 4.00 Dec. 15, 2009 Page 373 of 1558
REJ09B0181-0400