SH7080_09 Datasheet, PDF (474/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority: When the priority is set in fixed mode (CH0 > CH1) and
channel 1 is transferring in burst mode, if there is a transfer request to channel 0 with a higher
priority, the transfer of channel 0 will begin immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after
the channel 0 transfer has completely finished.
When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of
one transfer unit and the channel 1 transfer is continuously performed without releasing the bus
mastership. The bus mastership will then switch between the two in the order channel 0, channel
1, channel 0, and channel 1. Therefore, the bus state is such that the CPU cycle after the
completion of cycle steal mode transfer has been replaced with the channel 1 burst mode transfer.
(Hereinafter referred to as burst mode priority execution.)
This example is shown in figure 10.13. When multiple channels are operating in burst modes, the
channel with the highest priority is executed first.
When DMA transfer is executed in the multiple channels, the bus mastership will not be given to
the bus master until all competing burst transfers are complete.
CPU
DMA
CH1
DMA
CH1
DMA
CH0
CH0
DMA
CH1
CH1
DMA
CH0
CH0
DMA
CH1
DMA
CH1
CPU
CPU
DMAC CH1
Burst mode
DMAC CH0 and CH1
Cycle-steal mode
DMAC CH1
Burst mode
CPU
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Figure 10.13 Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes according to the specification shown in figure 10.3.
However, the channel in cycle steal mode cannot be mixed with the channel in burst mode.
Rev. 4.00 Dec. 15, 2009 Page 414 of 1558
REJ09B0181-0400