SH7080_09 Datasheet, PDF (1399/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 26 Power-Down Modes
26.5 Software Standby Mode
26.5.1 Transition to Software Standby Mode
This LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1.
However, software standby mode cannot be entered when the bus is released (low-level input to
BREQ pin). Execute the SLEEP instruction after halting the DMAC and DTC. In software
standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
The contents of the CPU registers and the data of the on-chip RAM remain unchanged. Some
registers of on-chip peripheral modules are, however, initialized. For details on the states of on-
chip peripheral module registers in software standby mode, refer to section 27.3, Register States in
Each Operating Mode. For details on the pin states in software standby mode, refer to appendix A,
Pin States.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. If the DMAC and DTC are operating, stop their operation.
4. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level
input to BREQ pin).
5. After setting the STBY bit in STBCR1 and the STBYMD bit in STBCR6 to 1, execute the
SLEEP instruction.
6. Software standby mode is entered and the clocks within this LSI are halted.
Rev. 4.00 Dec. 15, 2009 Page 1339 of 1558
REJ09B0181-0400