SH7080_09 Datasheet, PDF (898/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Receiving Serial Data (Asynchronous Mode):
Figures 16.7 and 16.8 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
[1] Receive error handling and
break detection:
Read ER, DR, BRK flags in
SCFSR and ORER
[1]
flag in SCLSR
ER, DR, BRK or ORER = 1?
Yes
No
Error handling
Read the DR, ER, and BRK
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the RXD
pin.
Read RDF flag in SCFSR
[2]
[2] SCIF status check and receive
data read:
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
All data received?
[3]
Yes
Clear RE bit in SCSCR to 0
End of reception
Read SCFSR and check that
RDF = 1, then read the receive
data in SCFRDR, read 1 from
the RDF flag, and then clear
the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can also be identified by
an RXIF interrupt.
[3] Serial reception continuation
procedure:
To continue serial reception,
read at least the receive
trigger number of receive data
bytes from SCFRDR, read 1
from the RDF flag, then clear
the RDF flag to 0. The number
of receive data bytes in
SCFRDR can be ascertained
by reading from the lower 8
bits of SCFDR.
Figure 16.7 Sample Flowchart for Receiving Serial Data
Rev. 4.00 Dec. 15, 2009 Page 838 of 1558
REJ09B0181-0400