SH7080_09 Datasheet, PDF (458/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and DAR
updated
*²
Bus mode,
*³
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
TE = 1
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer aborted
DEI interrupt request (when IE = 1)
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer end
Normal end
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 10.2 DMA Transfer Flowchart
Rev. 4.00 Dec. 15, 2009 Page 398 of 1558
REJ09B0181-0400