SH7080_09 Datasheet, PDF (43/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Figure 19.2
Figure 19.3
Figure 19.4
Figure 19.5
Figure 19.6
Figure 19.7
Figure 19.8
A/D Conversion Timing......................................................................................... 964
External Trigger Input Timing ............................................................................... 966
Example of 2-Channel Scanning............................................................................ 967
Definitions of A/D Conversion Accuracy .............................................................. 970
Definitions of A/D Conversion Accuracy .............................................................. 971
Example of Analog Input Circuit ........................................................................... 972
Example of Analog Input Protection Circuit.......................................................... 974
Section 20 Compare Match Timer (CMT)
Figure 20.1 Block Diagram of CMT ......................................................................................... 975
Figure 20.2 Counter Operation.................................................................................................. 980
Figure 20.3 Count Timing ......................................................................................................... 980
Figure 20.4 Timing of CMF Setting .......................................................................................... 981
Figure 20.5 Conflict between Write and Compare-Match Processes of CMCNT..................... 982
Figure 20.6 Conflict between Word-Write and Count-Up Processes of CMCNT..................... 983
Figure 20.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ...................... 984
Section 22 I/O Ports
Figure 22.1 Port A (SH7083) .................................................................................................. 1162
Figure 22.2 Port A (SH7084) .................................................................................................. 1163
Figure 22.3 Port A (SH7085) .................................................................................................. 1164
Figure 22.4 Port A (SH7086) .................................................................................................. 1165
Figure 22.5 Port B (SH7083)................................................................................................... 1177
Figure 22.6 Port B (SH7084, SH7085, SH7086)..................................................................... 1177
Figure 22.7 Port C (SH7083, SH7084, SH7085)..................................................................... 1183
Figure 22.8 Port C (SH7086)................................................................................................... 1184
Figure 22.9 Port D (SH7083, SH7084) ................................................................................... 1191
Figure 22.10 Port D (SH7085, SH7086) ................................................................................... 1192
Figure 22.11 Port E (SH7083)................................................................................................... 1199
Figure 22.12 Port E (SH7084)................................................................................................... 1200
Figure 22.13 Port E (SH7085)................................................................................................... 1201
Figure 22.14 Port E (SH7086)................................................................................................... 1202
Figure 22.15 Port F (SH7083, SH7084, SH7085) ..................................................................... 1211
Figure 22.16 Port F (SH7086) ................................................................................................... 1211
Section 23 Flash Memory
Figure 23.1 Block Diagram of Flash Memory......................................................................... 1217
Figure 23.2 Mode Transition of Flash Memory ...................................................................... 1218
Figure 23.3 Flash Memory Configuration ............................................................................... 1221
Figure 23.4 Block Division of User MAT............................................................................... 1222
Rev. 4.00 Dec. 15, 2009 Page xli of lviii
REJ09B0181-0400