SH7080_09 Datasheet, PDF (468/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.7 shows an example of DMA transfer timing in dual address mode.
CK
A29 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
RD
WRxx
DACKn
(Active-low)
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 10.7 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)
Rev. 4.00 Dec. 15, 2009 Page 408 of 1558
REJ09B0181-0400