SH7080_09 Datasheet, PDF (867/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
2
PER
0
R
Parity Error
Indicates a parity error in the data read from the next
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive parity error occurred in the next data
read from SCFRDR
[Clearing conditions]
• PER is cleared to 0 when the chip undergoes a
power-on reset
• PER is cleared to 0 when no parity error is present
in the next data read from SCFRDR
1: A receive parity error occurred in the next data read
from SCFRDR
[Setting condition]
• PER is set to 1 when a parity error is present in
the next data read from SCFRDR
Rev. 4.00 Dec. 15, 2009 Page 807 of 1558
REJ09B0181-0400